Solid-state imaging device having a counting unit and a comparison unit with switchable frequency band characteristics and imaging apparatus having the same

ABSTRACT

A solid-state imaging device includes the following. Pixels arranged in matrix converts received light into signal voltage. A column AD conversion unit, which includes a comparison unit and an up-down counting unit, converts signal voltage to digital signal. The comparison unit compares a value of signal voltage to a gradually changing value of reference signal voltage. The up-down counting unit counts, by one of down-counting and up-counting, a time period until the comparison result is reversed if the signal voltage is of a base signal component of each pixel at reset level, and counts, by an other of down-counting and up-counting, the time period if the signal voltage is of a superimposed signal component in which the base signal component is superimposed on a pixel signal component corresponding to an amount of light received by the pixel. The comparison unit has switchable kinds of frequency band characteristics.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation application of PCT International Application No.PCT/JP2012/006892 filed on Oct. 26, 2012, designating the United Statesof America, which is based on and claims priority of Japanese PatentApplication No. 2011-257530 filed on Nov. 25, 2011. The entiredisclosures of the above-identified applications, including thespecifications, drawings and claims are incorporated herein by referencein their entirety.

FIELD

The present disclosure relates to solid-state imaging devices andimaging apparatuses having the same.

BACKGROUND

For Analog to Digital (AD) conversion of Metal-Oxide-Semiconductor (MOS)image sensors, so-called single-slope AD conversion circuits have beenused. The single-slope AD conversion circuits convert a graduallychanging analog value of a reference signal voltage to a digital signalvalue according to information regarding a time period from when thereference signal voltage is generated to when a value relationshipbetween the reference signal voltage and a signal voltage is changed.

Referring to FIG. 9, the following describes a structure of aconventional solid-state imaging device disclosed in PatentLiterature 1. The conventional solid-state imaging device includessingle-slope AD conversion circuits provided for respective columns ofpixels.

As illustrated in FIG. 9, a solid-state imaging device 1001 includes apixel array 1010 where a plurality of pixels 1003 are arrayed in rowsand columns (in other words, two-dimensionally arrayed in a matrix).Each of the pixels 1003 includes a light-receiving element (an exampleof an electric charge generation unit) that outputs a signalcorresponding to an amount of incident light. Thereby, each of thepixels 1003 outputs a signal voltage. The solid-state imaging device1001 includes Analog Digital Converters (ADCs) each provided to acorresponding one of the columns of the pixels 1003.

More specifically, in the solid-state imaging device 1001, outside thepixel array 1010, there are provided: a drive control unit including avertical scan circuit 1014, a timing control circuit 1020, and ahorizontal scan circuit 1012; and a column processing unit 1026including column AD circuits 1025 each provided to a corresponding oneof the columns; a reference voltage generation unit 1027 that supplies aplurality of reference signal voltages Vref1 and Vref2 to the columnprocessing unit 1026 to be used in AD conversion.

Each of the column AD circuits 1025 includes a voltage comparison unit1252, a counter/data storage unit 1254, an AD conversion selectioncircuit 1253, a switch 1255, a switch 1256, and a capacitance 1257.

The drive control unit has a control circuit function of sequentiallyreading signals from the pixel array 1010. For example, the drivecontrol unit includes the horizontal scan circuit (column scan circuit)1012 that controls column addresses and column scanning; the verticalscan circuit (row scan circuit) 1014 that controls row addresses and rowscanning; and the timing control circuit 1020 having a function ofgenerating an internal clock.

Each of the pixels 1003 is connected to the vertical scan circuit 1014via a row control line 1015 used to select a row, and also connected tothe column processing unit 1026 via a column signal line 1019. Here, therow control line 1015 refers to an entire line from the vertical scancircuit 1014 to the pixels 1003.

The horizontal scan circuit 1012 has a function of a readout scan unitthat reads a count value from the column processing unit 1026 to acorresponding one of horizontal signal lines (not illustrated) via ahorizontal control line 1016 used to select a column.

Each of the horizontal scan circuit 1012 and the vertical scan circuit1014 includes, for example, a decoder, and starts scanning in responseto a control signal provided from the timing control circuit 1020. Thevertical scan circuit 1014 selects a row in the pixel array 1010 andsupplies a necessary pulse to the selected row. The horizontal scancircuit 1012 sequentially selects the column AD circuits 1025 in thecolumn processing unit 1026 so as to provide a signal of the selectedcolumn AD circuit 1025 to a corresponding one of the horizontal signallines (horizontal output lines). It should be noted that the horizontalsignal lines are provided in number corresponding to, for example, nbits (where n is a natural number) which the column AD circuit 1025 candeal with. For example, in the case of 10 bits (n=10), ten horizontalsignal lines are provided.

Furthermore, pixel signals outputted from the pixels 1003 in each columnare provided to a corresponding column AD circuit 1025 in the columnprocessing unit 1026 via a corresponding column signal line 1019. Eachof the column AD circuits 1025 in the column processing unit 1026receives analog signals of pixels 1003 in a corresponding column, andprocesses the received analog signals.

Here, the AD conversion performed by the column processing unit 1026adopts a method by which analog signals provided in parallel from thecolumns for each row are AD-converted by the column AD circuits 1025provided to respective columns, into digital signals in parallel foreach row. In this method, a technique of single slope integration (orramp signal comparison) AD conversion is used.

In the single slope integration AD conversion, a target analog signal isconverted to a digital signal based on a time period from when theconversion starts to when the reference signal voltage Vref1 or Vref2becomes equal to the target signal voltage. In principle, the singleslope integration AD conversion is performed in the following manner.Supply of ramp reference signal voltage Vref1 and Vref2 to a comparator(voltage comparator) is started, and counting (number count) by a clocksignal is also started at the same time. Then, an analog pixel signalprovided via the column signal line 1019 is compared to each of thereference signal voltages Vref1 and Vref2. Until a pulse signalindicates that an analog pixel signal is equal to each of the referencesignal voltages Vref1 and Vref2, the counter/data storage unit 1254keeps counting the clock counts.

CITATION LIST Patent Literature

-   [Patent Literature 1] Japanese Unexamined Patent Application    Publication No. 2011-41091.

SUMMARY Technical Problem

The conventional solid-state imaging device disclosed in PatentLiterature 1 performs the following AD conversion. In the AD conversion,according to a signal level of a pixel signal examined by the ADconversion selection circuit 1253, a switch to be used for each columnis selected between the switch 1255 and the switch 1256. Therefore, ifthe signal level of the pixel signal is high, the reference signalvoltage Vref1 having a sharp ramp (in other words, a large quantizationerror) is used, and restriction of a frequency band of the voltagecomparison unit 1252 using the capacitance 1257 is not performed (inother words, a speed is high) so as not to suppress noises. On the otherhand, if the signal level of the pixel signal is low, the referencesignal voltage Vref2 having a rather flat ramp (in other words, having asmall quantization error), and restriction of a frequency band of thevoltage comparison unit 1252 using the capacitance 1257 is performed (inother words, a speed is slow) so as to suppress noises.

As described above, the conventional solid-state imaging deviceincreases a speed of AD conversion, and reduces noises by restricting afrequency band of the voltage comparison unit.

However, in the conventional solid-state imaging device disclosed inPatent Literature 1, correlated sampling is not considered in the ADconversion circuit. The correlated sampling is performed in thefollowing manner. A “base signal” (a reset level of a pixel from which apixel signal has not yet been readout) provided from a pixel isAD-converted in a down-counting mode. Then, “pixel signal+base signal”(a signal level of the pixel from which a pixel signal has been readout)provided from the pixel is AD-converted in an up-counting mode.Therefore, a differential signal between the two AD-converted values isobtained (“pixel signal+base signal”−“base signal”) as a resultingAD-converted value of the pixel signal.

In other words, the conventional solid-state imaging device disclosed inPatent Literature 1 neither considers nor observes effects of suchcorrelated sampling by so-called up-down counting to cancel (a) KTCnoise caused by resetting the pixel unit, (b) various fixed patternnoises such as vertical lines caused by variations of AD conversiondelay, and (c) random noise caused mainly by a 1/f noise of lowfrequency.

Furthermore, the conventional solid-state imaging device has a followingproblems. In the conventional solid-state imaging device, a frequencyband of the voltage comparison unit is switched according to a signallevel of a pixel signal. Therefore, in the first AD conversion on “basesignal”, a signal level of a pixel signal is not certain. As a result,it is impossible to use the same frequency band and the same referencesignal ramp for the second AD conversion on “pixel signal+base signal”and the first AD conversion on “base signal”. Therefore, even if theconventional solid-state imaging device adopts correlated sampling, itis difficult to cancel fixed pattern noise.

The conventional solid-state imaging device has another problem.Although it is possible to determine a signal level of a pixel signal inthe first AD conversion if the AD conversion on “pixel signal+basesignal” is first performed, KTC noise caused by resetting are differentbetween the first AD conversion and the second AD conversion because“base signal” is not the same. Therefore, even if the conventionalsolid-state imaging device adopts correlated sampling, it is stilldifficult to cancel fixed pattern noise.

As described above, the conventional solid-state imaging device fails tosatisfy both (a) canceling of fixed pattern noise caused by correlatedsampling using up-down counting and (b) suppression of noise byrestricting a frequency band of the voltage comparison unit. In short,the conventional solid-state imaging device has a problem ofdeteriorating image quality due to noises.

In order to address the above problems, one non-limiting and exemplaryembodiment provides a solid-state imaging device capable of suppressingimage quality deterioration caused by noise.

Solution to Problem

In accordance with an aspect of the present invention for achieving theobject, there is provided a solid-state imaging device including: aplurality of pixels arranged in rows and columns, each of the pixelsconverting received light into a signal voltage; and a columnAnalog-to-Digital (AD) conversion unit configured to convert the signalvoltage to a digital signal, wherein the column AD conversion unitincludes: a comparison unit configured to determine, as a comparisonresult, which is greater between a value of the signal voltage and agradually changing value of a reference signal voltage; an up-downcounting unit configured to (i) count, by one of down-counting andup-counting, a time period until the comparison result of the comparisonunit is reversed if the signal voltage is a voltage of a base signalcomponent of each of the pixels at a reset level, and (ii) count, by another of the down-counting and the up-counting, a time period until thecomparison result of the comparison unit is reversed if the signalvoltage is a voltage of a superimposed signal component in which thebase signal component is superimposed on a pixel signal componentcorresponding to an amount of light received by the each of the pixels,and the comparison unit has plural kinds of frequency bandcharacteristics which are switchable.

With the above structure, it is possible to homogenize conversion gains,by using the same reference signal voltage for respective columns.Therefore, the conversion gains are not different from white balancegains assumed to be homogeneous (same) conversion gains. As a result, itis possible to reduce occurrence of color noise caused by coloring. Inaddition, by switching frequency band characteristics of the comparisonunit, it is possible to suppress random noise.

Accordingly, the solid-state imaging device according to an aspect ofthe present disclosure is capable of suppressing image qualitydeterioration caused by noise.

Advantageous Effects

The solid-state imaging device according to the present disclosure iscapable of suppressing image quality deterioration caused by noise.

BRIEF DESCRIPTION OF DRAWINGS

These and other advantages and characteristics will become apparent fromthe following description thereof taken in conjunction with theaccompanying Drawings, by way of non-limiting examples of embodimentsdisclosed herein.

FIG. 1 is a block diagram illustrating an overall structure of asolid-state imaging device according to Embodiment 1.

FIG. 2 is a circuit diagram illustrating of a detailed structure of apixel.

FIG. 3A is a circuit diagram illustrating an example of a detailedstructure of a voltage comparison unit.

FIG. 3B is a graph plotting frequency band characteristics of thevoltage comparison unit.

FIG. 4 is a time chart of processing performed by the solid-stateimaging device.

FIG. 5 is a block diagram illustrating an overall structure of asolid-state imaging device according to Embodiment 2.

FIG. 6 is a circuit diagram illustrating output impedance of a pixelaccording to Variation 1 of Embodiment 2.

FIG. 7A is an external view of an example of a video camera.

FIG. 7B is an external view of an example of digital still camera.

FIG. 8 is a block diagram illustrating a structure of an imagingapparatus according to Embodiment 3.

FIG. 9 is a block diagram illustrating a structure of a solid-stateimaging device according to an prior art.

DESCRIPTION OF EMBODIMENT(S)

The following describes embodiments and their variations in detail withreference to the Drawings.

It should be noted that all the embodiments and variations describedbelow are generic and specific examples of the present disclosure.Numerical values, shapes, materials, constituent elements, arrangementpositions and the connection configuration of the constituent elements,steps, the order of the steps, and the like described in the followingembodiments are merely examples. They are therefore not intended tolimit the present disclosure. Therefore, among the constituent elementsin the following embodiments and variations, constituent elements thatare not described in independent claims that show the most genericconcept of the present disclosure are described as elements constitutingmore desirable configurations.

Embodiment 1

A solid-state imaging device according to the present embodimentselects, in a down-counting period, a narrow band for frequencycharacteristics of a comparison unit, and selects the same narrowfrequency band in an up-counting period. Therefore, the solid-stateimaging device according to the present embodiment can suppress fixedpattern noise by performing correlated sampling. In addition, thesolid-state imaging device according to the present embodiment cansuppress random noise by restricting a frequency band of the comparisonunit. Moreover, the solid-state imaging device according to the presentembodiment can increase a speed of AD conversion by selecting a broadband for frequency characteristics of the comparison unit in a timeperiod before starting the down-counting period and in a time periodbefore starting the up-counting period.

The following describes a structure and processing of the solid-stateimaging device according to Embodiment 1 with reference to the Drawings.

FIG. 1 is a block diagram illustrating an overall structure of thesolid-state imaging device 1 according to Embodiment 1. The solid-stateimaging device according to the present embodiment includes a pixelarray 3, a vertical scan circuit 4, row control lines 5, column signallines 6, a readout current source group 7, an AD conversion unit 8, ahorizontal signal line 9, a horizontal scan circuit 10, horizontalcontrol lines 11, an output circuit 12, a timing control unit 13, areference signal generation unit 14, and a band selection unit 20.Although the functional blocks illustrated in FIG. 1 are arranged toonly one side of the pixel array 3, they may be arranged to both sidesof the pixel array 3.

The pixel array 3 includes a plurality of pixels 2 arranged in rows andcolumns. Each of the pixels 2 performs photoelectric-conversion onincident light to generate a signal voltage. More specifically, thepixel 2 generates: a base signal component Vrst that is a signal voltageat a pixel 2 at a reset level; and a superimposed signal componentVrst+Vsig in which the base signal component Vrst is superimposed on apixel signal component Vsig that is a signal voltage corresponding to anamount of light received by the pixel 2.

The vertical scan circuit 4 performs vertical scanning by sequentiallyselecting rows of the pixels 2 by sequentially activating the rowcontrol lines 5 according to signals provided from the timing controlunit 13. Signal voltages at the selected row are transferred to the ADconversion unit 8 via the column signal lines 6 corresponding to therespective columns and the readout current source group 7.

Each of the column signal lines 6 is provided to a corresponding one ofthe columns of the pixels 2 to transfer signal voltages outputted frompixels 2 in the corresponding column.

The readout current source group 7 includes readout current sources eachcorresponding to a corresponding one of the columns in the pixel array3. The readout current source group 7 provides the AD conversion unit 8with signal voltages which are outputted to the column signal line 6.

The AD conversion unit 8 AD-converts the signal voltages provided fromthe pixel array 3 to digital signals. More specifically, the ADconversion unit 8 includes a plurality of column AD conversion circuits17. Each of the column AD conversion circuits 17 s is provided to acorresponding one of the column signal lines 6, and converts a signalvoltage transferred via the corresponding column signal line 6 into adigital signal.

Each of the column AD conversion circuits 17 includes a voltagecomparison unit 15 and an up-down counter/data storage unit 16. Thevoltage comparison unit 15 compares a value of a signal voltage to agradually changing value of a reference signal voltage Vslope, therebydetermining, as a comparison result, which is greater between the valueof the signal voltage and the value of the reference signal voltageVslope. The voltage comparison unit 15 has narrow-band frequencycharacteristics and broad-band frequency characteristics which areswitchable. If the signal voltage compared to the reference signalvoltage Vslope is a voltage of a base signal component Vrst in eachpixel 2 at a reset level, the up-down counter/data storage unit 16counts down a time period until the comparison result is reversed. Onthe other hand, if the signal voltage compared to the reference signalvoltage Vslope is a voltage of a superimposed signal component Vrst+Vsigin which the base signal component Vrst is superimposed on a pixelsignal component Vsig corresponding to an amount of light received bythe pixel 2, the up-down counter/data storage unit 16 counts up a timeperiod until the comparison result is reversed. It should be noted thateach of the column AD conversion circuits 17 is an example of the columnAD conversion unit according to the aspect of the present disclosure.

The horizontal signal line 9 transfers, to the output circuit 12, thedigital signals provided from the AD conversion unit 8.

The horizontal scan circuit 10 performs horizontal scanning bysequentially selecting the columns of the column AD conversion circuits17 by sequentially activating the horizontal control lines 11 accordingto signals provided from the timing control unit 13. A digital signal ofa selected column is provided to the above-described horizontal signalline 9.

The output circuit 12 outputs a value of the digital signal transferredvia the horizontal signal line 9, to the outside of the solid-stateimaging device 1. The output circuit 12 is desirably, for example, ahigh-speed transfer circuit such as Low-Voltage Differential Signaling(LVDS). The output method, the circuit, and the structure of the outputcircuit 12 are not limited as long as the output circuit 12 can outputdigital signal values. Moreover, whether the values are outputtedsequentially or in parallel, how many output ports are provided, and thelike are not limited for the output circuit 12.

The timing control unit 13 is a circuit that controls times ofprocessing performed by each of the processing units. More specifically,for example, the timing control unit 13 instructs the vertical scancircuit 4 when to activate a target row control line 5, and instructsthe horizontal scan circuit 10 when to activate a target horizontalcontrol line 11. Furthermore, the timing control unit 13 instructs thereference signal generation unit 14 when to generate the referencesignal voltage Vslope, and instructs the band selection unit 20 when togenerate a band selection signal F_SEL.

Under the control of the timing control unit 13, the reference signalgeneration unit 14 generates the reference signal voltage Vslope for ADconversion to be used by the AD conversion unit 8, and provides the samereference signal voltage Vslope to the column AD conversion circuits 17.

Under the control of the timing control unit 13, the band selection unit20 selects frequency band characteristics of the voltage comparison unit15 included in each of the column AD conversion circuits 17, andprovides a band selection signal F_SEL to each of the column ADconversion circuits 17 to notify the selected frequency bandcharacteristics. More specifically, as the frequency bandcharacteristics for the voltage comparison unit 15, the band selectionunit 20 selects narrow frequency band characteristics (hereinafter,referred to also as “narrow band characteristics”) are selected in acounting period during which the up-down counter/data storage unit 16counts a time period of comparison for a base signal component Vrst andin a counting period during which the up-down counter/data storage unit16 counts a time period of comparison for a superimposed signalcomponent Vrst+Vsig. On the other hand, the band selection unit 20selects broad frequency band characteristics (hereinafter, referred toalso as “broad band characteristics”) in the other periods except theabove counting periods.

As described above, the solid-state imaging device 1 according to thepresent embodiment includes: a plurality of pixels 2 arranged in rowsand columns, each of the pixels converting received light into a signalvoltage; and a column Analog-to-Digital (AD) conversion unit 17 thatconverts the signal voltage to a digital signal. The column ADconversion unit 17 includes: a voltage comparison unit 15 thatdetermines, as a comparison result, which is greater between a value ofthe signal voltage and a gradually changing value of a reference signalvoltage Vslope; an up-down counting unit 16 that (i) counts, by one ofdown-counting and up-counting, a time period until the comparison resultof the voltage comparison unit 15 is reversed if the signal voltage is avoltage of a base signal component Vrst of each of the pixels 2 at areset level, and (ii) counts, by an other of the down-counting and theup-counting, a time period until the comparison result of the voltagecomparison unit 15 is reversed if the signal voltage is a voltage of asuperimposed signal component Vrst+Vsig in which the base signalcomponent Vrst is superimposed on a pixel signal component Vsigcorresponding to an amount of light received by the each of the pixels2. The voltage comparison unit 15 has plural kinds of frequency bandcharacteristics which are switchable. It should be noted that thevoltage comparison unit 15 corresponds to the comparison unit accordingto the aspect of the present disclosure, and that the up-downcounter/data storage unit 16 corresponds to the up-down count unitaccording to the aspect of the present disclosure.

With the above structure, by sharing the same reference signal voltageVslope among the columns, conversion gains are homogenized. As a result,the conversion gains are not different from white balance gains assumedto be homogeneous conversion gains. As a result, it is possible toreduce occurrence of color noise caused by coloring. In addition, byswitching frequency band characteristics of the voltage comparison unit15, it is possible to suppress random noise.

Thus, the solid-state imaging device 1 according to the presentembodiment can suppress image quality deterioration caused by noise.

Next, the structure of the solid-state imaging device 1 according to thepresent embodiment is described in more detail.

FIG. 2 is a circuit diagram illustrating a detailed structure of thepixel 2 in the solid-state imaging device 1 illustrated in FIG. 1. Eachof the pixels 2 is a so-called 4-transistor pixel, including aphotodiode (pixel) 30, a transfer transistor 31, an amplificationtransistor 32, a selection transistor 33, and a reset transistor 34.FIG. 2 illustrates a pixel 2 in the m-th row and a pixel 2 in the(m+1)th row. FIG. 2 also illustrates a column signal line 6 and areadout current source 7 a which are provided to a column includingthese pixels 2.

Serving as a row control line 5 for the m-th row, there are provided areset signal line RST_m, a pixel selection signal line SEL_m, and acharge transfer signal line TRG_m to supply respective signals from thevertical scan circuit 4 to the pixel 2 in the m-th row. Output terminalsof pixels 2 in the same column are connected to the same column signalline 6 provided to the column. A readout current source 7 a, which isprovided to each of the column signal lines 6, and an amplificationtransistor 32, which is in a row where a selection transistor 33 isconductive, form a source follower. In other words, the amplificationtransistor 32 is a transistor for providing a signal voltage to thecolumn AD conversion circuit 17.

It should be noted that the illustrated structure of the pixel 2 is anexample. The pixel 2 may be a so-called 3-transistor pixel without theselection transistor 33. The transistors included in the pixel 2 may bean NMOS transistor or a PMOS transistor. It is also possible that aplurality of column signal lines 6 are provided to a single column.

It should also be noted that the structure of the pixel 2 is not limitedas long as the pixel 2 can provide the column signal line 6 with asignal voltage provided from the photodiode 30. For example, althoughthe pixel 2 in FIG. 2 is so-called single-pixel single cell structure inwhich a single photodiode 30 is provided with a single transfertransistor 31 and a single amplification transistor 32. However, thepixel 2 may have a so-called multi-pixel single cell structure in whicha plurality of photodiodes 30 share a single transfer transistor 31 anda single amplification transistor 32. It should also be noted that thestructure of the readout current source 7 a is not limited, and may usea resistance load means (a resistor element or on-resistance of atransistor).

In the pixel 2 in the m-th row, first, the reset signal line RST_m makesthe reset transistor 34 conductive, thereby resetting a gate voltage ofthe amplification transistor 32, namely, a voltage of a so-calledfloating diffusion part. Subsequently, the pixel selection signal lineSEL_m makes the selection transistor 33 conductive. Thereby, a voltageat the reset floating diffusion part is provided, as a voltage Vrst(base signal component) of a reset level of the pixel 2 in the m-th row,to the column signal line 6 via the amplification transistor 32, andthereby supplied to the AD conversion unit 8 at the later stage to beAD-converted.

Furthermore, the photodiode 30 accumulates charges that are generated byphotoelectric conversion on light received during exposure. After apredetermined exposure period has passed, in the pixel 2 in the m-throw, the charge transfer signal line TRG_m makes the transfer transistor31 conductive, thereby transferring the accumulated charges in thephotodiode 30 to the floating diffusion part. The transferred chargesare provided, as a voltage (Vrst+Vsig) (base signal component+pixelsignal component) in which the voltage Vrst of the reset level of thepixel 2 in the m-th row is superimposed with a voltage Vsig of a signallevel of the pixel 2 in the m-th row corresponding to the received lightamount, to the column signal line 6 via the amplification transistor 32,and thereby supplied to the AD conversion unit 8 in the later stage tobe AD-converted.

As a result, the AD conversion unit 8 extracts a difference betweensignals resulting from two AD conversion operations, in other words,performs correlated sampling, so as to obtain a signal level of thepixel 2 in the m-th row which corresponds to the received light amount.In other words, by performing correlated sampling to extract adifference between (a) a base signal component Vrst that is a signalvoltage of a reset level of a pixel 2 and (b) a superimposed signalcomponent Vrst+Vsig in which the base signal component Vrst issuperimposed with a pixel signal component Vsig that is a signal voltagecorresponding to an amount of light received by the pixel 2, it ispossible to obtain the pixel signal component Vsig.

Furthermore, the correlated sampling can cancel (i) KTC noise includedin a base signal component Vrst that is a voltage of a reset level andcaused by resetting of the floating diffusion part, (b) various fixedpattern noises such as vertical lines caused by variations of ADconversion delay on respective columns, and (c) random noise causedmainly by 1/f noise of low frequency. It should be noted that, in thecorrelated sampling, in order to efficiently perform the noisecancellation, it is possible to perform a driving method using the sameresponse speed and the same frequency band characteristics betweendifferent AD conversion operations for different pixel signal levels.

It should be noted that the driving method is not limited to the above.Any driving method is possible as long as the correlated sampling isefficiently performed by providing the AD conversion unit 8 with (a) avoltage Vrst of a reset level of the pixel 2 in the m-th row and (b) avoltage (Vrst+Vsig) in which the voltage Vrst is superimposed with avoltage Vsig of a signal level in the m-th row which corresponds to areceived light amount.

Furthermore, in the present embodiment, it is also possible to provide asample hold unit that sample-holds a signal to be provided to the ADconversion unit 8. In this case, it is possible to achieve so-calledpipeline processing in which conversion of the AD conversion unit 8 andsignal reading from the pixel 2 to the column signal line 6 areperformed in parallel. As a result, the solid-state imaging device 1 canincrease a frame rate.

It should also be noted that in the present embodiment, it is alsopossible to provide a signal amplification unit, such as Auto GainControl (AGC), a so-called column amplifier, in the signal path from theoutput terminal of the pixel 2 to the input terminal of the ADconversion unit 8. This structure can increase a signal level of asignal inputted to the AD conversion unit 8. As a result, inputconversion Signal-to-Noise (S/N) in the AD conversion is improved, andthe solid-state imaging device 1 can enhance image quality. It should benoted that the column amplifier is desirably a so-called single-endinverter amplifier that drives constant-current loads in thesource-grounded amplifier circuit. However, the column amplifier is notlimited to the structure and may be other amplification means such as adifferential amplifier circuit.

Next, the structure and the AD conversion of the AD conversion unit 8are described.

As illustrated in FIG. 1, the AD conversion unit 8 is a single-slope ADconversion circuit. In the AD conversion unit 8, the column ADconversion circuits 17 provided to the respective columns convert aplurality of signal voltages provided from the column signal lines 6provided to the respective columns into digital signals at the sametime.

Each of the column AD conversion circuits 17 includes a voltagecomparison unit 15 and an up-down counter/data storage unit 16. Thevoltage comparison unit 15 has a function of switching frequency bandcharacteristics. The solid-state imaging device 1 includes a bandselection unit 20 that selects the frequency band characteristics of thevoltage comparison unit 15 according to a time of driving.

The reference signal generation unit 14 generates a reference signalvoltage (ramp waveform signal voltage) Vslope that is gradually changingas a time passes. The reference signal voltage Vslope may have a smoothsloping waveform or a stepped waveform. The waveform of the referencesignal voltage Vslope is not limited as long as the waveform is changedwith a certain ramp (inclination). The ramp of the reference signalvoltage Vslope may be positive or negative. The reference signalgeneration unit 14 may have a structure in which increasing ordecreasing code values are given to a Digital-Analog Converter (DAC) andoutputs of the DAC are filtered, or a structure in which an integralaction is performed using a capacitance element. However, the structureof the reference signal generation unit 14 is not limited as long as thereference signal generation unit 14 can generate a waveform that ischanged with a certain ramp. However, in order to homogenize conversiongains of the respective columns, the same reference signal voltageVslope is provided to the column AD conversion circuits 17 in all of thecolumns.

The voltage comparison unit 15 compares (a) a value of a signal voltagethat is provided to the column signal line 6 and converted to a digitalsignal, to (b) a gradually changing value of the reference signalvoltage Vslope provided to the voltage comparison unit 15, so as todetermine, as a comparison result, which is greater between the value ofthe signal voltage and the value of the reference signal voltage Vslope.

It should be noted that the structure of the voltage comparison unit 15is not limited as long as the voltage comparison unit 15 can compare asignal voltage of the column signal line 6 to the reference signalvoltage Vslope and switch frequency band characteristics. For example,the voltage comparison unit 15 may be not only a differential comparatorhaving a well-known offset cancel function, but also a differentialcomparator including a so-called chopper comparator or the like.

The up-down counter/data storage unit 16 counts, in AD conversion, atime period from when the voltage comparison unit 15 starts thecomparison until when the comparison result of the voltage comparisonunit 15 is reversed. In other words, the up-down counter/data storageunit 16 counts a time period from when the voltage comparison unit 15starts the comparison until when a value relationship between a signalvoltage of the column signal line 6 and the reference signal voltageVslope is changed (until when an output of the voltage comparison unit15 is reversed). More specifically, the up-down counter/data storageunit 16 performs AD conversion by counting clocks CK that have beeninputted from the start of the comparison to the change of valuerelationship between the signal voltage and the reference signal voltageVslope. After the AD conversion, the up-down counter/data storage unit16 holds a resulting digital signal value (count value). In this ADconversion, counting is performed twice. More specifically, an ADconversion operation is performed by counting down a time period ofcomparison for a voltage Vrst of a reset level, and another ADconversion operation is performed by counting up a time period ofcomparison for a voltage (Vrst+Vsig) in which the reset level voltageVrst is superimposed with a signal level voltage Vsig corresponding to areceived light amount. As a result, from difference information betweenthe two AD conversion operations, a signal level of the pixel 2 can bedetermined.

In other words, the up-down counter/data storage unit 16 obtains a pixelsignal component Vsig that is a signal voltage corresponding to anamount of light received by the pixel 2, by performing correlatedsampling for extracting a difference between (a) a base signal componentVrst that is a signal voltage of a reset level of the pixel 2 and (b) asuperimposed signal component Vsig+Vrst in which the base signalcomponent Vrst is superimposed on the pixel signal component Vsig.

In order to efficiently operate the correlated sampling and reducenoise, the band selection unit 20 outputs a band selection signal F_SELfor selecting the same narrow frequency band characteristics both in theup-counting period and in the down-counting period. In order to increasea speed of the AD conversion, the band selection unit 20 outputs a bandselection signal F_SEL for selecting broad-band frequencycharacteristics in a period before the down counting and in a periodbefore the up counting.

In other words, under the control of the timing control unit 13, theband selection unit 20 selects the frequency band characteristics of thevoltage comparison unit 15 in the column AD conversion circuit 17, so asto cause the voltage comparison unit 15 to switch the frequency bandcharacteristics to the selected frequency band characteristics. Morespecifically, the band selection unit 20 selects narrow bandcharacteristics both in a counting period in which the up-downcounter/data storage unit 16 counts a time period of comparison for thebase signal component Vrst and in a counting period in which the up-downcounter/data storage unit 16 counts a time period of comparison for thesuperimposed signal component Vrst+Vsig. On the other hand, the bandselection unit 20 selects broad band characteristics in the otherperiods except the counting periods.

Thereby, noise suppression using frequency band restriction can belimited only in the counting periods, and high-speed operations can beprioritized in the other operation periods. More specifically, if thevoltage comparison unit 15 has narrow frequency band characteristics (ifthe frequency band is restricted), random noise can be suppressed. Onthe other hand, if the voltage comparison unit 15 has broad-bandfrequency characteristics, AD conversion can be performed at a highspeed. Therefore, it is possible to achieve (a) suppression of fixedpattern noise by correlated sampling, (b) suppression of random noise byswitching the frequency band characteristics of the voltage comparisonunit 15, and (c) increase of a speed of the AD conversion.

It is also possible that the band selection unit 20 selects narrow bandcharacteristics in a part of the counting period for comparison for thebase signal component Vrst or a part of the counting period forcomparison for the superimposed signal component Vrst+Vsig, and selectsbroad band characteristics in a part of the period before startingcounting for comparison for the base signal component Vrst or a part ofthe period before starting counting for comparison for the superimposedsignal component Vrst+Vsig.

Next, the voltage comparison unit 15 is described in more detail withreference to FIGS. 3A and 3B. FIG. 3A is a circuit diagram illustratingan example of a detailed structure of the voltage comparison unit 15.FIG. 3B is a graph plotting the frequency band characteristics of thevoltage comparison unit 15.

First, as illustrated in FIG. 3A, the voltage comparison unit 15includes a differential comparison circuit 40 and offset cancelcapacitances 46 a and 46 b. The differential comparison circuit 40includes offset cancel switches 41 a and 41 b, a capacitance 42, aswitch 43, and a pre-charge unit 44. Although the pre-charge unit 44 maynot be provided, the provision of the pre-charge unit can furtherincrease a speed of the AD conversion as described later.

In the voltage comparison unit 15, according to a control signal ZERO ofan auto zero operation, the offset cancel switches 41 a and 41 b becomeconductive. Therefore, an operation point of the differential comparisoncircuit 40 is set, and an offset voltage at the differential comparisoncircuit 40 is held in the offset cancel capacitances 46 a and 46 b. As aresult, a comparison operation in which offset is canceled, namely,comparison operation including a so-called auto zero operation, isperformed.

Furthermore, according to the band selection signal F_SEL provided fromthe band selection unit 20, the voltage comparison unit 15 can switchthe frequency band characteristics.

More specifically, the voltage comparison unit 15 controls a conductivestate of the switch 43 according to a band selection signal F_SELprovided from the band selection unit 20, and controls connection of thecapacitance 42. The connection state of the capacitance 42 varies thefrequency band characteristics. In short, by switching the switch 43between a conductive state and a non-conductive state, the connectionstate of the capacitance 42 is switched. As a result, the frequency bandcharacteristics of the voltage comparison unit 15 are switched.

For example, if, as illustrated in FIG. 3B, the capacitance 42 isconnected to between differential output terminals of the differentialcomparison circuit 40, the frequency band characteristics become anarrow band. On the other hand, if the capacitance 42 is disconnectedbetween the differential output terminals of the differential comparisoncircuit 40, the frequency band characteristics become a broad band. Inother words, if the band selection unit 20 causes the switch 43 to beconductive, the frequency band characteristics of the voltage comparisonunit 15 become a narrow band. On the other hand, if the band selectionunit 20 causes the switch 43 to be non-conductive, the frequency bandcharacteristics of the voltage comparison unit 15 become a broad band

As described above, the voltage comparison unit 15 includes: (a) thedifferential comparison circuit 40 that compares a signal voltage to areference signal voltage; (b) the capacitance 42 having an end connectedto one of differential output terminals of the differential comparisoncircuit 40; and (c) the switch 43 that controlsconductive/non-conductive states between the other one of thedifferential output terminals of the differential comparison circuit 40and the other end of the capacitance 42. By switching between aconductive state and a non-conductive state of the switch 43, thefrequency band characteristics are switched.

Thereby, for example, by comparing the case where the capacitance isinserted between an output port of the voltage comparison unit 15 and aground or power source, it is possible to achieve narrower frequencyband characteristics with the same capacitance value.

Here, if the frequency band characteristics of the voltage comparisonunit 15 are set to a narrow band, the solid-state imaging device 1according to the present embodiment can relatively suppress noise forinput signals provided from pixels. In other words, in comparison to thecase where the frequency band characteristics of the voltage comparisonunit 15 are set to a broad band, more noise can be suppressed.

Therefore, when the band selection unit 20 selects narrow bandcharacteristics both in a counting period in which the up-downcounter/data storage unit 16 counts a time period of comparison for abase signal component Vrst and in a counting period in which the up-downcounter/data storage unit 16 counts a time period of comparison for asuperimposed signal component Vrst+Vsig, it is possible to suppressfixed pattern noise in the correlated sampling of the column ADconversion circuit 17.

On the other hand, if the frequency band characteristics are set to abroad band, it is possible to relatively increase a speed of a responseof the comparison operation, in other words, increase a speed of ADconversion. In other words, in comparison to the case where thefrequency band characteristics of the voltage comparison unit 15 are setto a narrow band, it is possible to increase a speed of response of thecomparison operation of the voltage comparison unit 15, therebyincreasing a speed of the AD conversion of the column AD conversioncircuit 17.

Therefore, if the band selection unit 20 selects broad bandcharacteristics in periods except the counting periods of the up-downcounter/data storage unit 16 for the comparison for the base signalcomponent Vrst and the superimposed signal component Vrst+Vsig, it ispossible to increase a speed of AD conversion of the column ADconversion circuit 17.

As described above, according to a band selection signal F_SEL providedfrom the band selection unit 20, the voltage comparison unit 15 selectsnarrow band characteristics both in a counting period in which theup-down counter/data storage unit 16 counts a time period of comparisonfor the base signal component Vrst and in a counting period in which theup-down counter/data storage unit 16 counts a time period of comparisonfor the superimposed signal component Vrst+Vsig, and selects broad bandcharacteristics in the other periods except the counting periods.

As a result, it is possible to suppress fixed pattern noise by thecorrelated sampling using up-down counting, and also possible toincrease a speed of the AD conversion.

Furthermore, the voltage comparison unit 15 includes the pre-charge unit44 that pre-charges an end of the capacitance 42 when the switch 43 isdisconnected. In other words, the voltage comparison unit 15 includesthe pre-charge unit 44 that pre-charges the capacitance 42 when theswitch 43 is disconnected to be non-conductive.

Thereby, when the frequency band characteristics of the voltagecomparison unit 15 are changed from broad band characteristics to narrowband characteristics, in other word, when the capacitance 42 is changedfrom a disconnected state to a connected state, it is possible toprevent transient response delay caused by a potential difference of thecapacitance 42 between before and after the connection. In other words,the pre-charge unit 44 can pre-charge a potential of the capacitance 42to decrease the potential difference of the capacitance 42 betweenbefore and after connection. Furthermore, it is possible to pre-charge,to the capacitance 42, the same voltage as the output voltage of thedifferential comparison circuit 40 immediately prior to connection, inother words, the same voltage as the voltage supplied to the capacitance42 by causing the switch 43 to be conductive.

In other words, in the present embodiment, in the case where thefrequency band characteristics of the voltage comparison unit 15 are abroad band, it is possible to pre-charge a voltage at a node indicatedas Cnode in FIG. 3A to be the same voltage as COUT1. More specifically,in a period during which the broad-band frequency characteristics areselected, the pre-charge unit 44 pre-charges a voltage at a terminal forcontrolling a conductive state and a disconnecting state of thecapacitance 42 for determining a band of the differential comparisoncircuit 40, into the same voltage as that of the connecting targetCOUT1, by disconnecting the capacitance 42. As a result, the voltage atCnode indicated in FIG. 3A is not changed between before and afterswitching of the frequency band characteristics according to the outputsignal F_SEL of the band selection unit 20. Thereby, it is possible tosuppress mixing of noise caused by disconnection of the capacitance 42,suppress a response delay, and further increase a speed of the ADconversion.

It should be noted that the means for switching the frequency bandcharacteristics which is described with reference to FIG. 3A is anexample. The structure of the switching means is not limited as long asthe frequency band characteristics are switchable according to a bandselection signal F_SEL provided from the band selection unit 20. Forexample, the switching means may be connected between the output port ofthe differential comparison circuit 40 and the ground, and capable ofcontrolling the connection.

In other words, it is possible that the voltage comparison unit 15includes: the differential comparison circuit 40 that compares a signalvoltage and a reference signal voltage Vslope; the capacitance connectedto a connection point between the differential comparison circuit 40 andthe up-down counter/data storage unit 16; and the switch that controls aconductive/non-conductive state between the output port of thedifferential comparison circuit 40 and the capacitance, and the voltagecomparison unit 15 switches the switch between a conductive state and anon-conductive state, thereby switching the frequency bandcharacteristics.

Thereby, for example, in comparison to the case where the frequency bandcharacteristics are switched using a bias current and an outputparasitic capacitance of the voltage comparison unit 15, the above casecan switch the frequency band characteristics of the voltage comparisonunit 15 with a higher accuracy and more easily.

As described above, the solid-state imaging device 1 according to thepresent embodiment is characterized in the following features. Insweeping a reference signal (hereinafter, referred to as a “referencesignal sweep”) for comparison for a reset level (namely, a base signal)and a reference signal sweep for comparison for a voltage in which thereset level is superimposed on a signal level (namely, base signal+pixelsignal), the frequency band characteristics of the differentialcomparison circuit 40 are set to be a narrow band (frequency bandcharacteristics except the broadest frequency band characteristics amongplural kinds of switchable frequency band characteristics of the voltagecomparison unit 15) according to a band selection signal F_SEL providedfrom the band selection unit 20. On the other hand, prior to start ofthe reference signal sweep, in other words, in a period before start ofcounting by the up-down counter/data storage unit 16, the frequency bandcharacteristics of the differential comparison circuit 40 are set to bea broad band.

Next, the present disclosure is described in more detail by referring tooperation times of the solid-state imaging device 1 according to thepresent embodiment. FIG. 4 is a time chart of processing performed bythe solid-state imaging device 1.

FIG. 4 illustrates times of: a signal voltage VSIG provided to thevoltage comparison unit 15 via the column signal line 6; a referencesignal Vslope generated by the reference signal generation unit 14; acontrol signal ZERO for controlling an auto zero operation of thevoltage comparison unit 15; a signal F_SEL indicating a band selected bythe band selection unit 20; a voltage cnode (voltage at a node Cnode) atone end of the capacitance 42; a voltage COUT1 at an output terminal ofthe differential comparison circuit 40; a voltage COUT2 at an outputterminal of the voltage comparison unit 15; and a count value of theup-down counter/data storage unit 16. It is assumed that F_SEL is HIGHwhen the band selection unit 20 selects narrow band characteristics asthe frequency band characteristics of the voltage comparison unit 15,and F_SEL is LOW when the band selection unit 20 selects broad bandcharacteristics as the frequency band characteristics of the voltagecomparison unit 15.

First, in a period from time t0 to time t1, an operation point of thedifferential comparison circuit 40 is set according to the controlsignal ZERO of the auto zero operation. During this period for settingthe operation point (hereinafter, referred to as an “operation pointsetting period”), the pixel 2 provides a reset level Vrst to thedifferential comparison circuit 40 via the column signal line 6.However, in this period, the AD conversion is not performed, and it isnot necessary to suppress noise. Therefore, it is not necessary to setthe frequency band characteristics of the differential comparisoncircuit 40 to be a narrow band. On the contrary, setting of thefrequency band characteristics of the differential comparison circuit 40to a narrow band extends a time period required to cause the outputvoltage COUT1 of the differential comparison circuit 40 to converge to avoltage at the operation point, namely, the operation point settingperiod.

Therefore, in the solid-state imaging device 1 according to the presentembodiment, in a period prior to start of a reference signal sweepincluding the operation point setting period of the differentialcomparison circuit 40, the frequency band characteristics of thedifferential comparison circuit 40 are set to a broad band according tothe output signal F_SEL of the band selection unit 20.

In other words, the band selection unit 20 selects broad bandcharacteristics in a period prior to start of counting for comparisonfor the base signal component Vrst.

As a result, it is possible to reduce an entire period required for ADconversion including the operation point setting period of thedifferential comparison circuit 40, thereby increasing a speed of the ADconversion.

It should be noted that, in FIG. 4, in order to surely fix an output ofthe differential comparison circuit 40 to have an initial polarity, in aperiod from time t2 to time t3, the reference signal voltage Vslope isadded with an initial voltage. Here, a period in which the outputvoltage COUT1 of the differential comparison circuit 40 responses to theadded initial voltage is influenced by the frequency bandcharacteristics of the differential comparison circuit 40. Therefore, inthe present embodiment, also in a period (from time t2 to time t3) inwhich an offset is added to the reference signal voltage Vslope, thefrequency band characteristics of the differential comparison circuit 40are set to a broad band. As a result, it is possible to further reducean entire time period required for AD conversion, thereby increasing aspeed of the AD conversion. In other words, in the period forinitializing the reference signal from time t2 to time t3, the bandselection unit 20 selects broad band characteristics.

Next, at time t3, a reference signal sweep for comparison for a resetlevel (namely, base signal component Vrst) is started, and the sametime, counting of the up-down counter/data storage unit 16 (in theexample of FIG. 4, down-counting) is also started, thereby performingsingle-slope AD conversion. Here, the band selection unit 20 sets theoutput signal F_SEL to HIGH so as to set the frequency bandcharacteristics of the differential comparison circuit 40 to a narrowband. In other words, in a counting period (from time t3 to time t4) forcomparison for the base signal component Vrst, the band selection unit20 selects narrow band characteristics and causes the voltage comparisonunit 15 to switch the frequency band characteristics to narrow bandcharacteristics.

It is therefore possible to produce effects of band restriction of thedifferential comparison circuit 40. By suppressing random noisecomponents, AD conversion can be performed with low noise.

After the AD conversion for the reset level, another AD conversion isperformed for a voltage Vsig+Vrst in which the reset level issuperimposed on a signal level. Therefore, it is necessary to set thereference signal Vslope back to the initial voltage. In addition, theoutput voltage COUT1 of the differential comparison circuit 40 alsoconverges to an initial voltage.

Therefore, in a period from time t4 to time t5, the reference signalvoltage Vslope is added with the initial voltage. As described above, aperiod in which the output voltage COUT1 of the differential comparisoncircuit 40 responses to the added initial voltage is influenced by thefrequency band characteristics of the differential comparison circuit40. Therefore, in the present embodiment, after the AD conversion forthe reset level, the frequency band characteristics of the differentialcomparison circuit 40 are set to a broad band according to the outputsignal F_SEL of the band selection unit 20. As a result, it is possibleto increase a speed of convergence of the output voltage COUT1 of thedifferential comparison circuit 40, and eventually increase a speed ofthe AD conversion. In other words, in the reference signalinitialization period from time t4 to time t5, the band selection unit20 selects broad band characteristics to cause the voltage comparisonunit 15 to switch the frequency band characteristics to broad bandcharacteristics.

Furthermore, at time t4, when the reference signal Vslope is set back tothe initial voltage, a voltage Vsig+Vrst in which the reset level issuperimposed on the signal level (namely, pixel signal component Vsig)is supplied from the pixel 2 to the differential comparison circuit 40via the column signal line 6.

After that, at time t5, a sweep of the reference signal Vslope isstarted, and at the same time, counting of the up-down counter/datastorage unit 16 (in the example of FIG. 4, up-counting) is also started,thereby performing single-slope AD conversion. Here, setting a directionof the counting of the up-down counter/data storage unit 16 to bedifferent from the direction used in the AD conversion for the resetlevel corresponds to subtracting the reset level Vrst from the voltageVsig+Vrst in which the reset level is superimposed on the signal level.As a result, a result of the AD conversion for the signal level Vsig canbe obtained. The above processing is generally called correlatedsampling. The correlated sampling can suppress (a) KTC noise caused byresetting the pixel unit, (b) various fixed pattern noises such asvertical lines caused by variations of AD conversion delay, and (c)random noise caused mainly by a 1/f noise of low frequency.

Therefore, in the present embodiment, the frequency band characteristicsof the differential comparison circuit 40 are set to the same narrowband characteristics in both up-counting and down-counting of theup-down counter/data storage unit 16. As a result, it is possible tomaximize effects of the correlated sampling.

In other words, the band selection unit 20 selects, in the countingperiod for comparison for the base signal component Vrst, narrowfrequency band characteristics from among plural kinds of frequency bandcharacteristics, while the band selection unit 20 selects, in thecounting period for comparison for the superimposed signal componentVrst+Vsig, the substantially same narrow frequency band characteristicsas selected in the counting period for the comparison for the basesignal component Vrst.

Therefore, it is possible to achieve both suppression of fixed patternnoise by the correlated sampling and suppression of random noise byswitching the frequency band characteristics of the voltage comparisonunit 15. As a result, image quality deterioration caused by noise can bedecreased.

It is also possible that the band selection unit 20 selects, in a partof the counting period for comparison for the base signal componentVrst, narrow frequency band characteristics, and selects, in a part ofthe counting period for comparison for the superimpose signal componentVrst+Vsig, the substantially same narrow frequency band characteristicsas selected in the part of the counting period for the comparison forthe base signal component Vrst.

It should be noted that, in the present embodiment, if increase of fixedpattern noise and random noise which are caused by insufficient effectsof the correlated sampling resulting from a different between thefrequency band characteristics in up-counting and the frequency bandcharacteristics in down-counting is within an acceptable range for thesolid-state imaging device 1, the two frequency band characteristics areconsidered as the substantially same narrow band characteristics.

It should be noted that, in the present disclosure, the down-countingand the up-counting in FIG. 4 may be reversed. More specifically, thefollowing is also possible. First, a reference signal sweep forcomparison for a reset level Vrst (namely, base signal) is started. Atthe same time, up-counting of the up-down counter/data storage unit 16is performed. Then, when the reference signal Vslope is set back to aninitial voltage, a voltage Vsig+Vrst in which the reset level issuperimposed on a signal level is supplied from a pixel to thedifferential comparison circuit 40 via the column signal line 6. Afterthat, sweeping of the reference signal Vslope is started, and at thesame time, down-counting of the up-down counter/data storage unit 16 isperformed.

As described above with reference to the drawings, the solid-stateimaging device according to the present embodiment selects the samenarrow frequency band characteristics in both the two AD conversionoperations. Thereby, the correlated sampling is efficiently operated,and noise suppression effects of the differential comparison circuit aremaximized. As a result, it is possible to suppress random noise andfixed pattern noise at maximum.

In other words, the solid-state imaging device 1 according to thepresent embodiment includes: a plurality of pixels 2 arranged in rowsand columns, each of the pixels converting received light into a signalvoltage; and a column Analog-to-Digital (AD) conversion unit 17 thatconverts the signal voltage to a digital signal. The column ADconversion unit 17 includes: a voltage comparison unit 15 thatdetermines, as a comparison result, which is greater between a value ofthe signal voltage and a gradually changing value of a reference signalvoltage Vslope; an up-down counting unit 16 that (i) counts, by one ofdown-counting and up-counting, a time period until the comparison resultof the voltage comparison unit 15 is reversed if the signal voltage is avoltage of a base signal component Vrst of each of the pixels 2 at areset level, and (ii) counts, by an other of the down-counting and theup-counting, a time period until the comparison result of the voltagecomparison unit 15 is reversed if the signal voltage is a voltage of asuperimposed signal component Vrst+Vsig in which the base signalcomponent Vrst is superimposed on a pixel signal component Vsigcorresponding to an amount of light received by the each of the pixels2. The voltage comparison unit 15 has plural kinds of frequency bandcharacteristics which are switchable.

As a result, fixed pattern noise can be suppressed by correlatedsampling using up/down counting. Furthermore, by selecting broad-bandfrequency characteristics in periods except the counting period forcomparison for the base signal component Vrst and the counting periodfor comparison for the superimposed signal component Vsig+Vrst, it ispossible to reduce a time required for periods except the countingperiods.

Furthermore, the same frequency band characteristics are selected bothin the up-counting period and in the down-counting period. Thereby, thesame conversion delay occurs in the both AD conversion operations. As aresult, it is possible to maximize noise cancellation effects of thecorrelated sampling, thereby obtaining images of high quality with lessvertical line noise and the like.

Moreover, broad-band frequency characteristics are selected in a periodbefore starting the reference signal sweep.

As a result, it is possible to increase a speed of a part of periodswhich does not contribute to noise characteristics of the AD conversionresults, thereby increasing a speed of the entire AD conversion. Inparticular, if broad-band frequency characteristics are selected in apart of periods where a voltage value of the reference signal Vslope isdramatically changed, it is possible to significantly increase a speedof the differential comparison circuit. As a result, it is possible toincrease a speed by reducing a time required for AD conversion, increasea frame rate of the solid-state imaging device 1, and increase thenumber of pictures continuously captured.

Furthermore, in the conventional solid-state imaging devices, aconversion time period is not different between when a frequency band ofthe voltage comparison unit is restricted and when the frequency band isnot restricted, so that plural kinds of reference signal voltages havingdifferent ramps (inclinations) are necessary. If a single referencesignal voltage is used, a time period for AD conversion on a column forwhich a narrow frequency band is selected is dominant. Therefore, it isnot necessary to select a broad frequency band according to a pixelsignal level.

On the other hand, if a plurality of reference signal voltages havingdifferent ramps (a ramp of one reference signal voltage=a ramp of theother reference signal voltage×2) are used, there is a gain differencethat is twice as large as a design value caused by a difference betweenramps of the reference signal voltages. Therefore, in order tohomogenize AD conversion gains in an image, it is necessary to convertthe conversion gain difference by, for example, adjusting a frequency ofa counting clock or performing digital calculation after the ADconversion.

However, when a plurality of reference signal voltages are used, aplurality of AD conversion gains, namely, ramps (inclinations) of therespective reference signal voltages are not completely identical to adesign value, even if the reference signal voltages are generated byrespective reference signal generation units having the completely samecircuit structure. Even if a difference between ramps of the referencesignal voltages is ideally double, in practice, the reference signalvoltages have a ramp difference of 2.1 times, for example. In this case,in a conversion operation on a conversion gain difference assumed tohave a double ramp difference, it is not possible to completely convertthe gain difference. The AD conversion gains are different depending onused reference signal voltages. Therefore, the AD conversion gains aredifferent from white balance gains assumed to be the same conversiongains. As a result, color noise occurs due to coloring, which seriouslydeteriorates image quality. The image quality deterioration caused bythe gain difference causes noise components with a fixed patterndepending on values of signals. Therefore, this image qualitydeterioration is a very serious problem unlike circuit (random) noise.

In contrast, the solid-state imaging device 1 according to the presentembodiment uses a single reference signal voltage Vslope for signalvoltages of each column. As a result, it is possible to prevent theproblem of a gain difference between columns. By eliminating such a gaindifference between the columns, the AD conversion gains are notdifferent from white balance gains assumed to be the same between thecolumns and between the pixels. As a result, it is possible to generatehigh-quality images with little image quality deterioration such ascoloring or color noise.

More specifically, the solid-state imaging device 1 according to thepresent embodiment is capable, with high satisfaction, of both (a)increase of a speed of the AD conversion and (b) reduction of bothrandom noise and fixed pattern noise.

Embodiment 2

The following describes a structure and processing of a solid-stateimaging device according to Embodiment 2 with reference to the Drawings,mainly explaining differences from Embodiment 1.

The solid-state imaging device according to Embodiment 2 has the almostsame structure as that of the solid-state imaging device 1 according toEmbodiment 1, but differs from the solid-state imaging device 1 inincluding a mode distinguishing circuit for selecting frequency bandcharacteristics of the voltage comparison unit 15 according to a mode.The mode distinguishing circuit receives a mode control signal andselects frequency band characteristics of the voltage comparison unit 15via the band selection unit 20 according to a mode instructed by thereceived mode control signal.

FIG. 5 is a block diagram illustrating an overall structure of thesolid-state imaging device according to Embodiment 2. It should be notedthat the same reference numerals in FIG. 1 are assigned to identicalstructural elements in FIG. 5.

As illustrated in FIG. 5, a solid-state imaging device 201 according toEmbodiment 2 has almost the same structure as that of the solid-stateimaging device 1 according to Embodiment 1. The solid-state imagingdevice 201 differs from the solid-state imaging device 1 in including amode distinguishing circuit 50. The mode distinguishing circuit 50determines, for each input mode control signal, whether or not a modeinstructed by the mode control signal includes a pixel signal additionoperation. If the mode includes a pixel signal addition operation, themode distinguishing circuit 50 selects broad-band frequencycharacteristics as frequency band characteristics of the voltagecomparison unit 15 via the band selection unit 20. On the other hand, ifthe mode does not include a pixel signal addition operation, the modedistinguishing circuit 50 selects narrow-band frequency characteristicsas frequency band characteristics of the voltage comparison unit 15 viathe band selection unit 20.

It should be noted that, in the present embodiment, the broad-bandfrequency characteristics correspond to the third frequency bandcharacteristics according to the aspect of the present disclosure, andthe narrow-band frequency characteristics correspond to the fourthfrequency band characteristics according to the aspect of the presentdisclosure.

The input mode control signal indicates, for example, details of themode, such as a High-Definition (HD) video mode or a still picture mode.In some modes, a pixel signal addition operation is performed to addsignals of two pixels together horizontally and vertically to eventuallyadd signals of four pixels together to be outputted, not to output pixelsignals in the number of pixels.

In general, in the pixel signal addition operation, for example, ifsignals of four pixels are to be added together, a resulting signalamount is four times. However, since random noise components remain onlyin the increase of a square root, a resulting noise amount is double.Therefore, an SN ratio is increased double in comparison to the casewithout the pixel signal addition operation.

Therefore, in a mode not including a pixel signal addition operation,the solid-state imaging device 201 according to the present embodimentmaximizes noise reduction by setting the frequency band characteristicsof the voltage comparison unit 15 to a narrow band. On the other hand,in a mode including a pixel signal addition operation, the pixel signaladdition operation can reduce noise, so that the solid-state imagingdevice 201 sets the frequency band characteristics of the voltagecomparison unit 15 to a relatively broad band to increase a speed of ADconversion. As a result, the solid-state imaging device 201 can achieveboth the noise reduction and the operation speed increase.

More specifically, in the same manner as described for the solid-stateimaging device 1 according to Embodiment 1, the solid-state imagingdevice 201 according to Embodiment 2 selects the same narrow-bandfrequency characteristics both in AD conversion on base signal componentand AD conversion on superimposed signal component. Thereby, thesolid-state imaging device 201 effectively performs correlated sampling,and maximizes effects of noise suppression of the differentialcomparison circuit to suppress random noise and fixed pattern noise atmaximum. Furthermore, in the present embodiment, in a mode includingpixel signal addition operation, the frequency band characteristics ofthe voltage comparison unit 15 are set to a relatively broad band,thereby increasing a speed of AD conversion. As a result, thesolid-state imaging device 201 according to the present embodiment canachieve both the noise reduction and the operation speed increase.

As described above, the solid-state imaging device 201 according toEmbodiment 2 differs from the solid-state imaging device 1 according toEmbodiment 1 in further including the mode distinguishing circuit 50that distinguishes a plurality of modes including at least one modeincluding a pixel signal addition operation that is an operation foradding together a plurality of signal voltages converted for differentpixels 2. According to results of the distinguishing of the modedistinguishing circuit 50, the band selection unit 20 selects broad-bandfrequency characteristics in at least one mode including the pixelsignal addition operation, and selects narrow-band frequencycharacteristics in the other mode not including the pixel signaladdition operation.

As a result, in an operation mode in which a pixel signal additionoperation suppresses random noise, high-speed operation has a priorityover noise reduction by frequency band restriction. In an operation modenot including a pixel signal addition operation and therefore notsuppressing random noise, noise reduction by frequency band restrictionhas a priority over the high-speed operation.

(Variation 1 of Embodiment 2)

A solid-state imaging device according to a variation of Embodiment 2has almost the same structure as that of the solid-state imaging device201 according to Embodiment 2. The solid-state imaging device accordingto the present variation differs from the solid-state imaging device 201in operation modes. The following describes the present variation,mainly explaining the differences from the solid-state imaging device201 according to Embodiment 2.

FIG. 6 is a diagram illustrating an output impedance Ro of anamplification transistor 32 in a pixel 2, for the sake of easyunderstanding of the present variation.

The solid-state imaging device according to the present variationincludes a mode distinguishing circuit 50 to select the frequency bandcharacteristics according to a mode. The mode distinguishing circuit 50receives a mode control signal indicating one of a plurality of modesincluding a pixel signal averaging operation, and selects the frequencyband characteristics of the voltage comparison unit 15 via the bandselection unit 20 according to the mode control signal.

In the pixel signal averaging operation, the solid-state imaging deviceaccording to the present variation causes, for example, an amplificationtransistor 32 and a selection transistor 33 in the m-th row and anamplification transistor 32 and a selection transistor 33 in the (m+1)throw to be conductive at the same time. As a result, base signals for thetwo rows, or a signal that is an average of the pixel signals areprovided to the same corresponding column signal line 6. In other words,the pixel signal averaging operation is performed by causing theamplification transistors 32 in the plurality of pixels 2 to beconductive at the same time.

Here, if a single readout current source 7 a is shared by a plurality ofamplification transistors 32, in general, one of the amplificationtransistors determines an output voltage. However, each of theamplification transistors 32 used in an image sensor stores data foreach pixel. Therefore, a size of the amplification transistor 32 isdecreased, and the output impedance Ro is increased. Furthermore, a gateof the amplification transistor 32 is driven by floating. Therefore, asignal is fed-back from a source to a gate with a capacitance componentbetween the gate and the source. Moreover, if a plurality ofamplification transistors 32 are set to be conductive at the same time,the pixel signal averaging operation is performed by resistance dividingand capacitance dividing.

The pixel signal averaging operation causes a plurality of amplificationtransistors 32 to be conductive at the same time. Therefore, a totalnumber of output impedances is Ro/the number of conductive amplificationtransistors 32. As a result, it is possible to decrease the outputimpedances, and reduce a time period required for convergence of a basesignal and pixel signal which are outputted via the amplificationtransistor 32 is reduced. It is thereby possible to keep more timeavailable for AD conversion.

Furthermore, in the present variation, in a mode including the pixelsignal averaging operation, by using such a time period available for ADconversion, noise is further suppressed. Therefore, in the modeincluding the pixel signal averaging operation, relatively narrow-bandfrequency characteristics are selected, in comparison to a modeincluding the pixel signal averaging operation.

Therefore, in the same manner as described for the solid-state imagingdevice 1 according to Embodiment 1, the solid-state imaging deviceaccording to Variation 1 of Embodiment 2 selects the same narrow-bandfrequency characteristics both in AD conversion on base signal componentand AD conversion on superimposed signal component. Thereby, thesolid-state imaging device effectively performs correlated sampling, andmaximizes effects of noise suppression of the differential comparisoncircuit to suppress random noise and fixed pattern noise at maximum.Furthermore, in the present variation, in a mode including a pixelsignal averaging operation, the frequency band characteristics of thevoltage comparison unit 15 are set to a relatively narrow band, therebyfurther suppressing noise without sacrificing a time period for ADconversion. As a result, the solid-state imaging device according to thepresent variation can achieve both the noise reduction and the operationspeed increase.

As described above, in the solid-state imaging device according to thepresent variation, the mode distinguishing circuit 50 distinguishes aplurality of modes including at least one mode including a pixel signalaveraging operation of causing a plurality of amplification transistors32 in a plurality of pixels 2 to be conductive at the same time. Then,according to the results of the distinguishing made by the modedistinguishing circuit 50, the band selection unit 20 selects frequencyband characteristics. In at least one operation mode not including apixel signal averaging operation, the band selection unit 20 selectsbroad-band frequency characteristics. In the other operation modeincluding the pixel signal averaging operation, the band selection unit20 selects narrow-band frequency characteristics. It should be notedthat the mode distinguishing circuit 50 corresponds to the operationmode distinguishing unit according to the aspect of the presentdisclosure.

Thereby, in an operation mode including a pixel signal averagingoperation that is an operation for increasing a speed of reading a pixelsignal component Vsig by decreasing output impedance by causing aplurality of amplification transistors 32 to be conductive, noisereduction by frequency band restriction has a priority. In contrast, inan operation mode not including the pixel signal averaging operation forincreasing a speed of reading pixel signals, a high-speed operation hasa priority. As a result, even in a plurality of operation modesincluding a pixel signal averaging operation, the solid-state imagingdevice according to the present variation can achieve (a) suppression offixed pattern noise by correlated sampling, (b) suppression of randomnoise by switching the frequency band characteristics of the voltagecomparison unit 15, and (c) increase of a speed of the AD conversion.

(Variation 2 of Embodiment 2)

A solid-state imaging device according to Variation 2 of Embodiment 2has the almost same structure as that of the solid-state imaging device201 according to Embodiment 2. The solid-state imaging device accordingto Variation 2 of Embodiment 2 differs from the solid-state imagingdevice 201 in that a different set of operation modes is used, that themode distinguishing circuit 50 distinguishes a plurality of modesincluding at least one of a video capturing mode and a still picturecapturing mode, and that the band selection unit 20 selects, accordingto a result of the distinguishing made by the mode distinguishingcircuit 50, broad-band frequency characteristics in the video capturingmode and selects narrow-band frequency characteristics in the stillpicture capturing mode. The following describes Variation 2 ofEmbodiment 2, mainly explaining the differences from the solid-stateimaging device 201 according to Embodiment 2.

In the video capturing mode, in most cases, a time period available forAD conversion is tightly restricted, for example, restricted to 60frames per second or 30 frames per second. On the other hand, in thestill-picture capturing mode, since capturing is performed for eachpicture, there is no tight restriction on frame rate, and therefore arelatively more time period is available for AD conversion.

Furthermore, in the video capturing mode, a plurality of pictures aresequentially displayed in a time axis direction. Therefore, human eyesare expected to serve as a visual filter suppressing random noise ofvideo in the time axis direction, so that noise in video is ratherrelatively tolerated. On the other hand, in the still-picture capturingmode, since a human sees only one picture as long as he/she likes, thereis a relatively severe requirement for preventing noise from a stillpicture.

Therefore, in the still-picture capturing mode, a time period availablefor AD conversion is used to deal with the relatively severe requirementfor the noise. Therefore, in the still-picture capturing mode,relatively narrow-band frequency characteristics are selected as thefrequency band characteristics of the voltage comparison unit 15 incomparison to the case of the video capturing mode. Moreover, in thevideo capturing mode, relatively broad-band frequency characteristicsare selected as the frequency band characteristics of the voltagecomparison unit 15 in comparison to the still-picture capturing mode. Asa result, a speed of AD conversion is increased.

Therefore, in the same manner as described for the solid-state imagingdevice 1 according to Embodiment 1, the solid-state imaging deviceaccording to Variation 2 of Embodiment 2 selects the same narrow-bandfrequency characteristics both in AD conversion on base signal componentand AD conversion on superimposed signal component. Thereby, thesolid-state imaging device effectively performs correlated sampling, andmaximizes effects of noise suppression of the differential comparisoncircuit to suppress random noise and fixed pattern noise at maximum. Inaddition, as the frequency band characteristics of the voltagecomparison unit 15, relatively narrow-band frequency characteristics areselected in the still-picture capturing mode and relatively broad-bandfrequency characteristics are selected in the video capturing mode. As aresult, it is possible to achieve both the noise reduction and theoperation speed increase.

As described above, the solid-state imaging device according toVariation 2 of Embodiment 2 includes the mode distinguishing circuitthat distinguishes a plurality of operation modes including at least oneof the video capturing mode and the still-picture capturing mode.According to a result of the determination made by the modedistinguishing circuit, the band selection unit selects broad-bandfrequency characteristics in the video capturing mode and selects thenarrow-band frequency characteristics in the still-picture capturingmode.

Therefore, a high-speed operation has a priority in the video capturingmode in which a frame rate is restricted and the high-speed operation isrequired, while noise reduction has a priority in the still-picturecapturing mode in which a frame rate is not required. As a result, eventhe solid-state imaging device that operates in the video capturing modeand the still-picture capturing mode is capable of achieving (a)suppression of fixed pattern noise by correlated sampling, (b)suppression of random noise by switching the frequency bandcharacteristics of the voltage comparison unit 15, and (3) increase of aspeed of the AD conversion.

Embodiment 3

The solid-state imaging devices according to the above embodiments andvariations are suitable as imaging devices (image input devices) inimaging apparatuses such as a video camera illustrated in FIG. 7A, adigital still camera illustrated in FIG. 7B, and a camera module formobile devices including a mobile phone.

FIG. 8 is a block diagram illustrating an example of a structure of animage apparatus. As illustrated in FIG. 8, the image apparatus accordingto the present embodiment includes: an optical system including a lens61; an imaging device 62; a camera signal processing circuit 63; asystem controller 64; and the like. The lens 61 forms image of imagelight emitted from a subject, on an imaging area of the imaging device62. The imaging device 62 converts the image light, which has beenformed as the image by the lens 61, into electric signals for eachpixel, thereby generating an image signal. The imaging device 62 is thesolid-state imaging device according to any one of the above-describedembodiments and variations.

The camera signal processing circuit 63 performs various signalprocesses on the image signal provided from the imaging device 62. Thesystem controller 64 controls the imaging device 62 and the camerasignal processing circuit 63.

Thus, the imaging apparatus according to the present embodiment includesthe imaging device 62 capable of decreasing deterioration of imagequality which is caused by noise.

Although the solid-state imaging device and the image apparatusaccording to the present disclosure have been described based on theabove embodiments and variations, the present disclosure is not limitedto the embodiments and variations. Those skilled in the art will bereadily appreciate that various modifications and combinations of thestructural elements in the different embodiments and variations arepossible without materially departing from the novel teachings andadvantages of the present disclosure. Accordingly, all suchmodifications and combinations are intended to be included within thescope of the present disclosure.

For example, the frequency band characteristics of the voltagecomparison unit 15 are not limited to the narrow-band frequencycharacteristics and the broad-band frequency characteristics, but may bethree different kinds of frequency band characteristics. In this case,it is possible that, in at least a part of a counting period forcomparison for the base signal component Vrst, the band selection unit20 selects frequency band characteristics except the broadest frequencyband characteristics from among the various kinds of frequency bandcharacteristics, and in at least a part of a counting period forcomparison for the superimposed signal component Vrst+Vsig, the bandselection unit 20 selects substantially the same frequency bandcharacteristics as selected in at least the part of the counting periodfor comparison for the base signal component Vrst.

It is also possible that, in at least a part of a counting period forcomparison for the base signal component Vrst and in at least a part ofa counting period for comparison for the superimposed signal componentVrst+Vsig, the band selection unit 20 selects the first frequency bandcharacteristics from among three or more kinds of frequency bandcharacteristics, and in at least a part before the counting period forthe comparison for the base signal component Vrst and in at least a partbefore the counting period for the comparison for the superimposedsignal component Vrst+Vsig, the band selection unit 20 selects, fromamong the three or more kinds of frequency band characteristics, thesecond frequency band characteristics that are broader than the firstfrequency band characteristics.

It is further possible that, according to a result of determination madeby the mode distinguishing circuit 50, in at least one operation modenot including the pixel signal addition operation, the band selectionunit 20 selects the third frequency band characteristics from amongthree or more kinds of frequency band characteristics, and in the othermode including the pixel signal addition operation, the band selectionunit 20 selects, from among the three or more kinds of frequency bandcharacteristics, the fourth frequency band characteristics that arenarrower than the third frequency band characteristics.

It is further possible that, according to a result of determination madeby the mode distinguishing circuit 50, in at least one operation modeincluding the pixel signal averaging operation, the band selection unit20 selects the third frequency band characteristics from among three ormore kinds of frequency band characteristics, and in the other operationmode not including the pixel signal averaging operation, the bandselection unit 20 selects, from among three or more kinds of frequencyband characteristics, the fourth frequency band characteristics that arenarrower than the third frequency band characteristics.

It is further possible that, according to a result of determination madeby the mode distinguishing circuit 50, in the video capturing mode, theband selection unit 20 selects the third frequency band characteristicsfrom among three or more kinds of frequency band characteristics, and inthe still-picture capturing mode, the band selection unit 20 selects,from among the three or more kinds of frequency band characteristics,the fourth frequency band characteristics that are narrower than thethird frequency band characteristics.

It should also be noted that the processing units in the solid-stateimaging device according to each of the above-described embodiments andvariations are typically implemented into a Large Scale Integration(LSI) which is an integrated circuit. These may be integratedseparately, or a part or all of them may be integrated into a singlechip.

The technique of integrated circuit is not limited to the LSI, and itmay be implemented as a dedicated circuit or a general-purposeprocessor. It is possible to use a Field Programmable Gate Array (FPGA)that can be programmed after manufacturing the LSI, or a reconfigurableprocessor in which connection and setting of circuit cells inside theLSI can be reconfigured.

It should also be noted that at least a part of the functions andstructures of the solid-state imaging devices according to theabove-described embodiments and variations may be combined.

It should also be noted that all the numerical numbers used in the abovedisclosure are examples for explaining the present disclosure in detail,and the present disclosure is therefore not limited to the numericalnumbers. Furthermore, the logical levels expressed as HIGH/LOW and theswitching states expressed as ON/OFF are examples for explaining thepresent disclosure in detail. It is possible to produce the same effectsas described in the present disclosure by using other combinations oflogical levels or different combinations of switching states which aredifferent from the examples in the present disclosure. It should also benoted that an n-type, a p-type, and the like of the transistors areexamples for explaining the present disclosure in detail. It is possibleto produce the same effects as described in the present disclosure byreversing the types. It should be noted that the connection relationshipbetween the structural elements are examples for explaining the presentdisclosure in detail, and the present disclosure is therefore notlimited to the connection relationship to achieve above-describedfunctions.

It should be noted that dividing of the functional blocks in the blockdiagrams is an example. It is possible to implement a plurality offunctional blocks into a single functional block, divide a singlefunctional block into a plurality of blocks, or cause a part of functionof a functional block to be performed by a different functional block.It should be noted that similar functions of a plurality of functionalblocks may be performed by a single hardware or software in parallel orin time-sharing.

It should be noted that a MOS transistor is used in the above-describeddescription, but any other kind of a transistor may be used.

It should be noted that the circuit structures illustrated in theabove-described circuit diagrams are examples, and the presentdisclosure is not limited to the circuit structures. In other words, itis also possible to use not only the above-described circuit structuresbut also any other circuits achieving the functions characterized in thepresent disclosure. For example, the present disclosure includes acircuit structure in which an element such as a transistor, a resistanceelement, a capacitance element, or the like is connected to an elementin series or in parallel as long as the circuit structure can providethe same function as that of the above-described circuit structures. Inother words, the expression “connecting” in the above embodiments andvariations is not limited to connection of two terminals (nodes) inseries. It is also possible to connect two terminals (nodes) to eachother via an element, as long as the same function as that in thepresent embodiments and variation can be produced.

INDUSTRIAL APPLICABILITY

The present disclosure is useful for solid-state imaging devices andimaging apparatuses, and useful in digital still cameras, digital videocameras, and the like in which, in particular, a high speed and highimage quality are required.

The invention claimed is:
 1. A solid-state imaging device comprising: aplurality of pixels arranged in rows and columns, each of the pixelsconverting received light into a signal voltage; and a columnAnalog-to-Digital (AD) conversion unit configured to convert the signalvoltage to a digital signal, wherein the column AD conversion unitincludes: a comparison unit configured to determine, as a comparisonresult, which is greater between a value of the signal voltage and agradually changing value of a reference signal voltage; an up-downcounting unit configured to (i) count, by one of down-counting andup-counting, a time period until the comparison result of the comparisonunit is reversed if the signal voltage is a voltage of a base signalcomponent of each of the pixels at a reset level, and (ii) count, by another of the down-counting and the up-counting, a time period until thecomparison result of the comparison unit is reversed if the signalvoltage is a voltage of a superimposed signal component in which thebase signal component is superimposed on a pixel signal componentcorresponding to an amount of light received by the each of the pixels,and the comparison unit has plural kinds of frequency bandcharacteristics which are switchable.
 2. The solid-state imaging deviceaccording to claim 1, further comprising a band selection unitconfigured to (i) select one kind of frequency band characteristicsamong the plural kinds of the frequency band characteristics, and (ii)cause the comparison unit to use the one kind of the frequency bandcharacteristics, wherein the band selection unit is configured to (i)select, in at least a part of the time period counted for the basesignal component, frequency band characteristics except broadestfrequency band characteristics from among the plural kinds of thefrequency band characteristics, and (ii) select, in at least a part ofthe time period counted for the superimposed signal component, frequencyband characteristics which are substantially same as the frequency bandcharacteristics selected in the at least the part of the time periodcounted for the base signal component.
 3. The solid-state imaging deviceaccording to claim 2, wherein the band selection unit is configured to:select a first kind of frequency band characteristics in the at leastthe part of the time period counted for the base signal component and inthe at least the part of the time period counted for the superimposedsignal component; and select a second kind of frequency bandcharacteristics which is broader than the first kind of frequency bandcharacteristics in at least a part of a time period before starting thetime period counted for the base signal component and in at least a partof a time period before starting the time period counted for thesuperimposed signal component.
 4. The solid-state imaging deviceaccording to claim 2, further comprising an operation modedistinguishing unit configured to distinguish a plurality of operationmodes including at least one operation mode including a pixel signaladdition operation by which a plurality of signal voltages converted indifferent pixels among the pixels are added together, wherein the bandselection unit is configured to, according to a result of thedistinguishing of the operation mode distinguishing unit, select a thirdkind of frequency band characteristics in the at least one operationmode including the pixel signal addition operation, and select a fourthkind of frequency band characteristics which is narrower than the thirdkind of frequency band characteristics in an other operation mode notincluding the pixel signal addition operation among the operation modes.5. The solid-state imaging device according to claim 2, wherein thepixels include amplification transistors, respectively, each of theamplification transistors outputting the signal voltage, the solid-stateimaging device further comprises an operation mode distinguishing unitconfigured to distinguish a plurality of operation modes including atleast one operation mode including a pixel signal averaging operation bywhich at least two of the amplification transistors in the pixels areset to be simultaneously conductive, wherein the band selection unit isconfigured to, according to a result of the distinguishing of theoperation mode distinguishing unit, select a third kind of frequencyband characteristics in an other operation mode not including the pixelsignal averaging operation among the operation modes, and select afourth kind of frequency band characteristics which is narrower than thethird kind of frequency band characteristics in the at least oneoperation mode including the pixel signal averaging operation.
 6. Thesolid-state imaging device according to claim 2, further comprising anoperation mode distinguishing unit configured to distinguish a pluralityof operation modes including at least one of a video capturing mode anda still-picture capturing mode, wherein the band selection unit isconfigured to, according to a result of the distinguishing of theoperation mode distinguishing unit, select a third kind of frequencyband characteristics in the video capturing mode, and select a fourthkind of frequency band characteristics which is narrower than the thirdkind of frequency band characteristics in the still-picture capturingmode.
 7. The solid-state imaging device according to claim 1, whereinthe comparison unit includes: a comparison circuit that compares thesignal voltage to the reference signal voltage; a capacitance connectedto a connection point between the comparison circuit and the up-downcounting unit; and a switch connected in series with the capacitance,thereby controlling a conductive state and a non-conductive statebetween an output terminal of the comparison circuit and thecapacitance, wherein the switch switches between the conductive stateand the non-conductive state to switch the plural kinds of the frequencyband characteristics.
 8. The solid-state imaging device according toclaim 1, wherein the comparison unit includes: a differential comparisoncircuit that compares the signal voltage to the reference signalvoltage; a capacitance having an end connected to one of differentialoutput terminals of the differential comparison circuit; and a switchthat controls a conductive state and a non-conductive state between another one of the differential output terminals of the differentialcomparison circuit and an other end of the capacitance, and wherein theswitch switches between the conductive state and the non-conductivestate to switch the plural kinds of the frequency band characteristics.9. The solid-state imaging device according to claim 7, wherein thecomparison unit further includes a pre-charge unit configured topre-charge the capacitance in blocking which is the non-conductive stateof the switch.
 10. An imaging apparatus comprising the solid-stateimaging device according to claim 1.